Digital portions of integrated circuit designs consist generally of memories (i.e. flip flops/latches) for storing one of two logic states and connected gates (i.e. Boolean logic) for performing logical operations on the logic states stored in the memories. An N input logic gate may receive input from N memories via N separate wires. Moore""s Law predicts that the number of transistors per square inch on integrated circuits doubles each 18 months. Thus, potentially the number of wires between memories and logic gates may double each 18 months. As the density of integrated circuits tracks Moore""s Law, the wiring within integrated circuit emerges as a serious obstacle to the advancement of semiconductors. Also, as the number of signaling wires increase, power consumption of integrated circuits, related to charging and discharging of wiring capacitance, also increases and emerges as another serious obstacle to the advancement of semiconductors.
The present invention provides novel quad-state logic elements for use with quad-state memory elements to reduce the wiring density of integrated circuits. The present invention, among other features described herein, advantageously provides reduced wiring interconnects between memories and logic elements, resulting in higher speed, higher density, and lower power integrated circuit designs.